I gave each tool 3 runs of each build stage to generate an average. The stopwatch was stopped as soon as the final line of the process was printed. The stopwatch was started when I clicked the last button in the GUI before the process starts (which was the dialog box’s ok button for both C sim and cosim) or when I hit return after issuing the vivado_hls -f script.tcl command. I used a basic stopwatch test to time the execution of the 3 build stages first using the GUI and then using a Tcl script to invoke the equivalent command. Xilinx offers a sin/cos function as part of the HLS math libraries but writing one out offered the chance to compare build performance at a couple of different stages of the design process. The test design used was a quickly knocked together floating point implementation of a sin function which uses a Taylor Series approximation.
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To explore these claims in a better way than just collecting anecdotal evidence I put together a rather un-scientific test to compare the execution times of the 3 most common HLS build processes: C simulation, C synthesis and cosimulation. Beyond raw processing speed I would also suggest that once adapted to working with the tool’s command line environment then the reduction in time spent clicking around in what is often (at least on Linux) a frustratingly laggy GUI, also offers a significant improvement in productivity! The underlying HLS processes are free to run at improved speeds because fewer overheads are required to maintain the GUI, open and close reports as they are generated and replaced, and capture and present every log message as it happens. One of the big advantages of working on the command line is the gain in performance of the tool. Once you have an optimised solution with a build process you are happy with then you can add the commands you need into a Tcl script and move to a scripted build process.
![download vivado 2017.4 hls download vivado 2017.4 hls](https://www.mdpi.com/electronics/electronics-09-01132/article_deploy/html/images/electronics-09-01132-g001.png)
Execute one or more of the build phases (c simulation, synthesis, cosim, etc).Īnd then probably iterate around modifying your source/directives and running builds.Specify a top level function for synthesis.Vivado HLS Help Output Vivado HLS Help Outputįor most simple projects the interactive workflow would look very familiar: Once in the interactive environment you can use the help command to list all the commands available and drill down into more detailed help info on each individual command. Or to execute a scripted batch run use: vivado_hls -f script.tcl To drop into an interactive session use: vivado_hls -i To use it you can just add arguments to the vivado_hls command used to launch the GUI. Vivado HLS has a Tcl interface for scripting or interactive use on the command line. Fortunately the tool runs on a powerful underlying Tcl base which allows us to move to the command line to unleash the full power and performance of the tool.
![download vivado 2017.4 hls download vivado 2017.4 hls](https://static.wixstatic.com/media/3b5532_4e7b5b9e2a184b06841ea3745e5d97fb~mv2.png)
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However, more advanced users or simply those who have worked with the tool for professional FPGA development for just a few weeks will start to realise the limitations of the GUI. A relatively simple GUI and some reasonable support documents mean anybody can jump in and get started with the tool. Xilinx’s High Level Synthesis package, Vivado HLS, is an excellent tool for rapidly developing complex IP cores for FPGA designs.